Mixing Symbolic and Ternary Simulation Techniques for the Verification of Processor-Based Systems
Flávio Miana, Claudionor N. Coelho, Patricia Nattrodt, Antônio Otávio Fernandes, Julio C. D. de Melo · 1997
We present a new technique to support processor validation and verification in absence of information when modeling reactive systems. Current processor validation techniques will not tolerate absence of information for some of its registers. In order to overcome this problem we combine symbolic simulation with temary logic simulation techniques. We exemplify our technique by simulating an Application Specific lnstruction Processor(ASIP) core with its embedded logic.