ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration
Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao · 2023
Verification typically consumes the majority of the time in the hardware development cycle. Primarily this is because multiple iterations to debug hardware using software simulation is extremely time-consuming. While FPGAs can be utilised to accelerate the simulation, existing methods either provide limited visibility of design details, or are expensive to check against a reference model dynamically at the system level.