A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash Memory
Hyun-Woo Kim, Seungwon Baek, Jaehong Song, Taigon Song · 2022 19th International SoC Design Conference (ISOCC) · 2022
Process-in Memory (PIM) is a scheme to enhance the processing speed in artificial intelligence (AI) by reducing the data bottle neck that occurs between the processor and memory. Typical PIM schemes focus on developing optimal paths between CPU and SRAM/DRAM. However, SRAM/DRAM based PIM may not be the optimal solution for cases where the data size for processing can easily be beyond the capacity of SRAM/DRAM. Thus, we propose a PIM scheme for NAND flash memory that shares the cache register. Our scheme significantly reduces the data transfer inside the memory hierarchy and reduces the runtime by −41.6% compared to DRAM PIM scheme. Compared to NAND flash scheme, we reduce the runtime by −34.6%