Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA
Monalisa Das, Babita Jajodia · 2022 19th International SoC Design Conference (ISOCC) · 2022
The requirements of hardware design for large integer polynomial multiplications is the need of the hour in various cryptographic fields involving large computational complexities. Schoolbook multiplication, being a common alternative is presented in this paper for implementation. A highly optimized Schoolbook multiplier is proposed, which is much faster than the traditional ones. The overall performance of the algorithm is evaluated using Area-Time-Product (ATP). Hardware implementation of the proposed schoolbook multiplication architecture is done using Virtex-7 FPGA device in Xilinx ISE platform.