FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives
Monalisa Das, Babita Jajodia · 2022 19th International SoC Design Conference (ISOCC) · 2022
Modern cryptographic algorithms demand the use and necessity for large integer polynomial multiplications. However for large input operand size of multipliers, the complexity of the hardware design arises in terms of space and time. Thus, in this paper efforts has been made to design an efficient polynomial multiplier by implementing a hybrid Karatsuba multiplication algorithm. The overall performance of the proposed design is measured using Area-Time-Product (ATP). Hardware implementation of the proposed architecture is done using Virtex-7 FPGA device in Xilinx ISE platform.