Impact on the Performance of North Bridge I/O Peripheral Component Interconnect Express Block in Physical Design Flow Considering Two Different Synthesis Corners at below 10nm Technology Node
Neha Karna, JagannadhaRao Arisankula, Satish Maheshwaram · 2022 IEEE International Symposium on Smart Electronic Systems (iSES) · 2022
Shrinking technology node improves the performance of the device but also makes the design process a lot more difficult. The primary objective of this paper concentrates on the physical implementation of a functional block in SOC and to conduct a detailed analysis on Speed, Area, Power, leakage, timing, and violation in two different synthesis corners (SC) i.e. SS0p65 and TT0p65 of physical design flow in ASIC design and understanding which synthesis corner is effective for designing the chip. In speed- wise TT0p65 SC is good as the clock period is 851ps whereas it is 1159ps for SS0p65 SC, but the area consumption is better in SS0p65 SC i.e. 43.77% whereas it is 46.875% for TT0p65 SC.