Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks
Juneeth Kumar Meka, Shrinidhi Venkatesh, Ranga R. Vemuri · 2022 IEEE International Symposium on Smart Electronic Systems (iSES) · 2022
The logic encryption methodology to hardware security introduces key inputs and key gates such that the circuit functionality is obfuscated unless the correct key is applied. The satisfiability-based (SAT) attack was shown to quickly unlock several logic encryption schemes. In this paper, we propose the generation of scalable synthetic benchmark sets to meet feature specifications in terms of the number of inputs, outputs and gates, composition of gate types, connectivity among gates and the number of levels of logic. We use these benchmarks to experimentally analyze the effectiveness of the SAT attack against a simple logic encryption scheme as the several circuit design parameters are varied. The results show the impact of the proportion of xor/xnor gates and circuit depth on the effectiveness of the SAT attack even when a simple encryption method is used. These results suggest guidelines for secure logic design and underline the importance of benchmarking using circuits that are appropriate for the application.