Impact analysis of virtual channels and Buffers on different Network-on-chip configurations
V. Lakshmi Kiranmai, B. K. N. Srinivasarao · 2022 IEEE International Symposium on Smart Electronic Systems (iSES) · 2022
Network-on-Chip (NoC) is a promising on-chip in-terconnection network that facilitates effective communication between the cores of complex Multi-Processor System-on-Chip (MPSoC) architectures. NoC combined with three-dimensional (3D) integration of MPSoCs is capable of meeting the MPSoCs' high performance requirements. Virtual channels (VCs) and buffers play a significant role among the numerous significant parameters that affect NoC performance. In this paper, 3D Mesh is evaluated with varying VC sizes and buffer sizes. Various asymmetric Mesh configurations have been proposed. In addition, 3D Mesh has been evaluated and compared for various symmetric and asymmetric VC and buffer configurations, as well as for various traffic patterns. The analysis provides the foundation for determining the optimal number of virtual channels and buffers for a network simulating a traffic pattern. Mesh layouts with asymmetric organisation of buffer resources have resulted in a reduction in the layout's area while providing comparable latency and throughput performance to its symmetrical baseline counterpart.