Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core
Rahul Kumar Chaurasia, Anirban Sengupta · 2022 IEEE International Symposium on Smart Electronic Systems (iSES) · 2022
This paper presents a novel approach for the exploration of security-design cost tradeoff for signature-based security methodologies used for detective control against intellectual property (IP) piracy/counterfeiting for digital signal processing (DSP) IP cores. The proposed approach offers low-cost hardware design architectural solutions for secured IP cores using particle swarm optimization (PSO). In the proposed approach, three different hardware security methodologies such as IP facial biometrics, encrypted-hashing and IP watermarking have been integrated with the PSO framework for exploring the hardware architecture tradeoffs of security-design cost for different DSP applications. The results of the presented approach include (i) analysis of low-cost architectural resource configuration, (ii) impact of signature strength on security-design cost fitness value and (iii) register count of the DSP IP core and (iv) security parameter such as probability of co-incidence for various security methodologies for varying (scalable) signature strength.