Ternary Logic Full Adder Circuit Using 3×1 Multiplexer
C. Venkataiah, M. Chennakesavulu, Ningampalli Ramanjaneyulu, Y. Mallikarjuna Rao, Anchula Sathish, Manjula Jayamma · Zenodo (CERN European Organization for Nuclear Research) · 2023
In this paper, a new ternary adders which are fundamental components of ternary addition, are presented. An algorithm is applied for synthesis that combines a geometrical representation with unary operators of multi valued logic which has taken from the previous researchers. The geometric demonstration enables scanning suitably to obtain simple sum-of-products expressions in terms of unary operators. Further, designed a full adder circuit of ternary logic using ternary 3×1 multiplexer using CNTFETs which is synthesized using the presented algorithm which has given the better performance than the conventional ones. A simulator tool has been used to simulate all the designed digital circuits. The proposed circuit has taken the very less number of transistors so that the complexity and power consumptions has been reduced. Further calculated the average power consumption for all the proposed designs.