FPGA implementation of the convolution coding method for industrial automation
M. S. Godwin Premi, N. Anusha, S. Kuzhaloli, Gnanaseelan Joselin Retna Kumar, M. Rajmohan · AIP conference proceedings · 2023
The FPGA-based encoder’s performance was investigated. Given the significant number of digital communication apps to store and retrieve data these days, this information should be transmitted and received with few errors. Forward Error Correction (FEC) is a critical component of a wireless communication system. Several encryption techniques have been tested, and the error is vastly varied. The convolution technique is used to correct errors during data transfer. Convolutional encoders must give AN output in the form of register style with defined locations in the register. The regions where the region is wholly organized are also depicted as rods. The faucets area indicates likely state transitions, where 2(L+1) is the number of states for a particular code. In this example, L denotes the length of the register. The best approach to defeat data corruption in digital communication channels is to fix code mistakes using these facts. The FPGA device was used in the hardware implementation of the Convolutional encoder. For performance analysis, Xilinx ISE is employed.