High Performance Area Efficient Scalable In-Place Real Valued FFT
A. Padmavathi, G. L. Sumalata · Advances in transdisciplinary engineering · 2023
An approach for formulating an area-latency and optimized architecture for an in RFFT is outlined in this study. In this paper, modified butterfly block with an addition of re programmable clock divider for generation of variable clock has been proposed. Because of its numerous uses in traditional digital signal processing and other developing domains, efficient computing of the real-valued Fast Fourier transform (RFFT) has got attention in recent years. Scalable in-place RFFT structure for larger inputs and efficiency with high throughput which is an important scenario that leads to the increase in size of memory and accessing issues of storage memory. A butterfly block, that does the computations of butterfly unit per clock period, is typical in an in-place FFT configuration. Study suggests that the in-place FFT can significantly improve the butterfly block structures and thereby providing reduction in parameters such as area occupancy and time delay. However, by changing the structure of butterfly blocks at higher input implementations, fourier transform calculations can be made such that good efficiency is obtained. Every application has several modules that run at different speeds, that needs clock which can be programmable according to the application’s parameters. To address this, a reprogrammable clock divider was implemented, and the parameters efficiency was studied and determined to be improved timing and area to existing implementations. The proposed method is implemented using Xilinx ISE 14.7 and the area, delay of existing and implemented designs are compared.