Novel Power Grid Architecture To Reduce IR Drop And Prevent Electromagnetic Interference
Ajay Sharma, Rishi Bhooshan, Raza Imam · 2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) · 2022
With technology scaling and increased design complexity in terms of higher performance and power with increased system on a chip integration leading to high IR drop causing higher delay which leads to timing failure in the chip and causing higher Electromagnetic interference (EMI) causing design failure in the system. Here in this paper, we propose a novel power grid architecture to create complete ground shield enclosure all over the die to prevent electromagnetic interference in the system and to reduce the IR drop in the chip to avoid system failure.