Hardware Data Prefetch for XiangShan Processor
Yuhan Zhu, Jiachun Zheng, Shuyan Ding, Lunbo Li · 2022 7th International Conference on Integrated Circuits and Microsystems (ICICM) · 2022
XiangShan, a rising star of RISC-V-based processors proposed by Chinese Academy of Science, is famous for its high performance and agile methodology. At present, the second-generation Yanqi Lake architecture of XiangShan has already reached the frequency of 2GHz at the 14nm process node, which ranks the first in the field of open-source RISC-V-based processors. One of the key approaches that contribute to its high performance is prefetch. A timely and accurate prefetcher can effectively eliminate cache misses and thus hide memory access latency. Aiming at the specific environment of XiangShan, out-of-order and parallel, a stride-based prefetcher for the L1DCache is achieved on the Yanqi Lake structure of XiangShan. Serious benchmarks from SPEC2006 were run on XiangShan, the result of which demonstrates that our prefetcher improves the performance of XiangShan by an average of 2.5% and up to 13.3%.