A Low BER Adaptive Sequence Detection Method for High-Speed NRZ Data Transmission
Chaolong Xu, Mingche Lai, Fangxu Lv, Liquan Xiao, Luo Zhang, Xingyun Qi, Yang Ou · 2022 7th International Conference on Integrated Circuits and Microsystems (ICICM) · 2022
To reduce the decision bit error rate (BER) caused by inter symbol interference (ISI) which become more severe as the baud rate of serializer/deserializer (SerDes) interface increases in high-performance computer (HPC) or data center networks, a novel low BER adaptive maximum likelihood sequence estimation (AMLSE) algorithm and its realizable circuit structure for high-speed ADC+DSP SerDes receiver are proposed. In additional, the viterbi algorithm (VA) is adopt to reduce the computational complexity, and the sliding block (SB) technique is proposed to cut the continuous input symbol stream into sliding blocks to achieve parallel decoding and continuous output of symbols in limited resources. An adaptive ISI parameters acquisition algorithm based on an improved zero-forcing (ZF) algorithm is combined to obtain the channel ISI parameters without special training sequence in initialization. The simulation results show that the maximum likelihood sequence estimation (MLSE) method can reduce the BER by up to more than two orders of magnitude and at least by half over DFE for five different fading levels SerDes channels as the baud rates changing from 12G to 56G. While the BER of the AMLSE method is reduced by up to three orders of magnitude and at least by two-thirds relative to ADFE under the same experimental conditions. The adaptive parameters can converge as fast as near 1000 unit interval (UI).