A Proposition to Effective Execution of Power-On Test Case Script over SoC under Post-Silicon-Validation
Tania Singh, Pawan Kumar Verma, Ansh Verma, Rajesh Verma · 2022 IEEE 6th Conference on Information and Communication Technology (CICT) · 2022
Post-Silicon-Validation (Po-Si-Val) plays a significant role in System-on-Chip (SoC) designing technique. Integrated circuits are created during manufacturing where there are many bugs that remain undetected during pre-silicon phase, here Po-Si-Val comes into picture. Various functional errors and electrical faults get detected and debugged during post-Silicon phase. As the first silicon sample arrives it is the responsibility of the Po-Si-Val team to validate the chips. This paper describes the effective execution of power-on test case script, debug techniques and debug tools that facilitate the bug-free chips to get successfully powered on. It also aims at understanding from where the problem arrives and what should be the correct approach to solve it. A power-on test case results are also attached which provides insight of the poweron debug.