Design and implementation of a carry-save full adder in quantum-dot cellular automata
Melika Amiri, Massoud Dousti, Majid Mohammadi · Research Square · 2022
Abstract Adders are one of the most widely used circuits in microprocessors. These circuits can also be used in various arithmetic operators. Adders are generally made in standard CMOS technology. However, at the nanoscale, CMOS technology faces some issues, such as less control over the gate and high current leakage. Quantum-dot cellular automata (QCA) can be employed to implement the next generation of digital electronic circuits. The present study proposes a carry-save adder in QCA technology for the first time. To the best of our knowledge, no QCA-based carry-save adder has been designed and examined to date. The simulation results show the superior performance of the proposed design over the state-of-the-art ripple-carry adders, with at least two QCA clocks faster addition operation even in the worst-case scenario. The proposed QCA-based adder has significantly higher speed and lower power consumption than its CMOS-based counterpart. The manufacturability of the design is substantially improved. In addition, our proposed full adder requires only 62 cells and the proposed full adder–subtractor requires only 521 cells. The proposed full adder–subtractor occupies 0.62 µm2. A design and simulation tool for QCA-based circuits, QCADesigner, is used to analyze the proposed designs.