MIPS Based 32-Bit RISC Processor with Thermal Management Unit and Flexible Pipelining Structure
Pammi Vijay Bharath, Boddepalli SanthiBhushan · 2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON) · 2022
Reduced Instruction Set Computer (RISC) uses a minimal set of highly optimized instructions to support our day to day computations. It is based on Harvard architecture with separate program and data memories. In general, the 32-bit RISC processor uses a fixed 5-stage pipelining to enhance the processing speed, however some instructions doesn't require all the 5-stages, hence there is still scope to enhance the processing speed. The present paper proposes a flexible 5-stage pipelining technique for a simple MIPS based 32-bit RISC processor to reduce the data dependency and processing time, along with the usual thermal management unit for hardware reliability and clock gating for power conservation. The RISC architecture has different types of instruction sets like Register type (R - type), Immediate type (I - type) and Jump type (J - type), and uses a 6-bit opcode for the 32-bit instructions. The proposed flexible pipelining mechanism switches between 4-stage pipelining and 5-stage pipelining according to the requirement of the instruction to be executed. The standard model and the proposed model with flexible pipelining, thermal management unit and clock gating are implemented with help of Xilinx Vivado 2020.2, a hardware description software. The proposed design offers higher processing speed, enhanced thermal stability, and dynamic power conservation in comparison to the standard 32-bit RISC processor.