Low Power Implementation of Compensated and Sharpened CIC Decimation Filter
P. K. Neeraja, T. S. Bindiya, Raghu C.V. · 2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON) · 2022
This paper presents implementation of minimax Sharpened Cascaded Integrator Comb (SCIC) decimation filter using polyphase decomposition. By employing polyphase decomposition, which is an efficient parallel processing technique, the power consumption of the CIC filter realization is significantly reduced at the cost of increased area. To enhance the passband characteristics of the SCIC filter, a multilplier-less compensator is cascaded. The ASIC synthesis result demonstrate that the polyphase realization results reduction in the total power consumption. This makes the design useful for low power sampling rate conversion (SRC) applications.