Unit cell mismatch scrambling method for high-resolution unary DAC based on virtual 3D layout
Dan Yao, Xuanyan Bai, Shogo Katayama, Anna Kuwana, Kazuyuki Kawauchi, Haruo Kobayashi, Kouji Hirai, Akira Suzuki, Satoshi Yamada, Tomoyuki Kato, Ritsuko Kitakoga, Takeshi Shimamura, Gopal Adhikari, Nobuto Ono, Kazuhiro Miura, Shigeya Yamaguchi · IEICE Electronics Express · 2022
The paper studies a unit cell mismatch scrambling method for a high-resolution unary DAC based on virtual 3-dimensional (3D) layout, to improve its spurious-free dynamic range (SFDR) for communication applications. This can be implemented with relatively simple interconnections and scrambling circuits, compared to that based on the 2-dimentional (2D) layout.