1542 Gbps Fully Pipelined Fast-SSC Decoding of Polar Codes
Alireza Hasani, Łukasz Łopaciński, Milos D. Krstic, Eckhard Grass · 2022 IEEE 33rd Annual International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC) · 2022
Polar codes are one of the candidates as a Forward-Error Correction (FEC) scheme for next-generation high-throughput communication systems. Successive Cancellation (SC) is one of the main decoding algorithms for decoding polar codes. In this paper, a fully pipelined fast Simplified SC (SSC) decoding architecture is proposed which proves a throughput of 1542 Gb/s in a 28 nm CMOS ASIC technology. This architecture is fully pipelined in the sense that sequences are decoded successively in consecutive clock cycles. The implementation results after the design Place&Route show improvements in terms of decoding throughput, clock frequency, core area, and energy efficiency compared with the state-of-the-art.