MINIMIZATION OF PROPAGATION DELAY OF CMOS INVERTER DRIVING AN RC LOAD
Ratan Kumar Debnath, Mohammad Ismat Kadir, Jharna Mandal · Khulna University Studies · 1999
The propagation delay of a signal through resistive network in large chips can limit the circuit performance. In order to develop a repeater design methodology, a complementary metal-oxide-semiconductor (CMOS) inverter driving an RC load is presented. By using Sakurai’s short channel a-power law model of transistor operation, the inverter model is applied to the problems of repeater in order to determine the reduced delay inserted along a RC line. For a typical RC load (R =1K, C =1pF), this repeater model exhibits less error as compared to a dynamic circuit simulator (SPICE).