AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks
Prabuddha Chakraborty, Swarup Bhunia · 2022
The modern horizontal semiconductor supply chain has introduced a plethora of security threats targeting the integrity and confidentiality of hardware intellectual properties (IPs) and integrated circuits (ICs). Threats, such as reverse engineering, cloning, tampering, extraction of design intent have given rise to serious concerns for both the user and the producer of microelectronic devices. Logic locking, a recently proposed methodology, aims to defend against some of these threats through strategic logic gate insertions (key gates) and structural modifications. However, we observed that most existing logic locking techniques are vulnerable to structural analysis attacks. Furthermore, there is no technique available to quantify the robustness against structural analysis attacks of logic locking techniques. Based on these observations, we have developed a set of artificial intelligence guided evaluation frameworks and metrics to identify structural (SAIL, SIVA) and joint structural-functional (SURF) vulnerabilities in locked designs and quantify them. We have also developed a learning-guided logic locking framework, LeGO, that iteratively hardens a design against a set of known attacks with the possibility of expanding this attack database over time as new attacks are discovered. SAIL, SURF, and SIVA have opened up a new research area on structural attack vulnerability analysis of logic locking, while LeGO serves as a building block for developing the next generation of AI-guided logic locking techniques.