The Implementation of Video Cipher Engine in FPGA
Lijun Liu · 2022 5th International Conference on Data Science and Information Technology (DSIT) · 2022
In the video system, a variety of different encryption engines are usually stacked in the FPGA to meet the system requirements for multiple encryption functions, which results in a large waste of FPGA resources. And because this structure is difficult to dynamically allocate the bandwidth of different algorithms according to the requirements of the system, it further aggravates the consumption of FPGA resources. According to the characteristics of video transport stream, this paper introduces a video encryption engine with pipeline structure. The encryption engine can support video data encryption standard DES, triple DES (3DES) and DVB common scrambling algorithm (DVB-CSA) at the same time, and can support electronic codebook (ECB), cipher block chaining (CBC) and reverse cipher block cipher (RCBC) encryption modes at the same time. It can also dynamically allocate bandwidth in different encryption algorithms and modes according to system requirements. The encryption engine can support simultaneous encryption of up to 32 transport stream packets, which can meet the performance requirements of the system line rate, while greatly reducing the requirements for FPGA resources.