Low-Complexity AES Architectures Resilient to Power Analysis Attacks
Jingbo Zhou, Elsayed Elgendy, Eslam Yahya Tawfik, Xinmiao Zhang · 2022
The advanced encryption standard (AES) is the current standard for symmetric-key cipher. To protect AES implementations from correlation power analysis (CPA) side-channel attacks (SCAs), many countermeasures have been proposed. However, existing approaches have large area overheads. This paper proposes two low-complexity techniques for AES to resist CPA attacks. By exploiting generalized dual ciphers, alternative conversions are utilized to substantially simplify all the involved constant matrix multiplications. Additionally, a multiplicative masking scheme utilizing simple constant multipliers is developed for AES designs used in resource-constraint applications. FPGA implementation results on a Xilinx XC7a200t device show that the proposed design with four Sboxes achieves 11.1% area reduction and 89.2% clock frequency increase compared to the best prior architecture without sacrificing CPA-attack resistance. In addition, the proposed multiplicative masking scheme not only keeps the resistance to CPA attacks, but also reduces the area by 52.6% and increases the clock frequency by 29.7% in a single-Sbox design compared to the previous scheme.