ISPLock: A Hybrid Internal State Locking Method Using Polymorphic Gates
Nikhil Saxena, Ranga R. Vemuri · 2022
Protecting Integrated Circuits (IC) from various attacks emerged as an important concern in recent years. Logic Encryption and Layout Camouflaging are two prominent meth-ods for IC protection. Many attacks to thwart these protection schemes have also emerged. The satisfiability (SAT) attack can defeat many logic locking schemes and can recover the correct key. Most existing SAT-resilient logic locking methods result in low output corruption rate. Emerging polymorphic gates allow the gate to be programmed to perform one of several logic functions. This work presents a new hybrid encryption scheme, named ISPLock (Internal State Polymorphic Locking). ISPLock makes use of polymorphic gates with an overall high corruption rate as well as SAT-resiliency. The method first selects certain internal nodes from the circuit and, then, determines an internal state of the selected nodes using a simulator. It replaces all selected gates with polymorphic gates and, based on the simulator output, it camouflages the internal states using polymorphic gates. The camouflaged internal state will be used to corrupt the functionality of the primary outputs. The resultant locked circuit is resilient against the SAT attack as well as several other attacks and results in high output corruption rates. Experimental results demonstrating these results using standard benchmark circuits are presented.