Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array
Lu Zhang, Dejun Mu, Yuxuan Huang, Jingyu Wang, Yifan He, Yaolei Li, Lizhou Liu, Kaiwei Zou, Huazhong Yang, Yongpan Liu · IEEE Transactions on Circuits & Systems II Express Briefs · 2022
Neural Network (NN) accelerators are widely used in many scenarios, including computer vision, speech recognition, automatic driving, etc. The trained weights of NNs are considered confidential properties due to their commercial value, thus becoming the potential targets for hardware reverse-engineering intruders. In this brief, we propose a low-cost, high-security, easy-to-deploy countermeasure for convolutional neural network (CNN) systolic array against weight reverse-engineering through power side channels. This countermeasure utilizes the clock frequency-switching and phase-shifting techniques to mitigate the power side channels. We further make a design space exploration to trade-off between Side-Channel Analysis (SCA) security and performance by leveraging the non-ideality of CMOS device. The experimental results show that the proposed countermeasure achieves an 81.6% absolute correlation reduction, thus incurring more than$100\times $power trace consumption (more secure) while maintaining the MAC (multiply-and-accumulate) blocks work at the Pareto-optimal frequencies (Pareto faster).