Reliable Quantum-dot Cellular Automata Coplanar Adder and Subtractor for Multi-bit Designs
Anantharaj Thalaimalai Vanaraj, K. Raja Sekar, R Marshal, Anand Venkitachalam, G Lakshminarayanan · 2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT) · 2022
Arithmetic and computational operations rely largely on addition and subtraction. Computational speed in many applications is determined by the speed of adders and subtractors. Quantum-dot Cellular Automata (QCA) nanotechnology can compute at extremely high speed due to its electron repulsion based communication and computation. Fault tolerance is a vital parameter of importance in QCA. Fault tolerance is improved by compensating the size and latency of the circuit. In this work, reliable designs of adder and subtractor with smaller Carry and Borrow latency are proposed. The faster generation of Carry and Borrow without compromising the reliability makes them an ideal choice for multi-bit operations as they will generate the outputs faster compared to reliable QCA adder and subtractor designs. Validation is carried out by using QCADesigner.