Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
Yan‐Fu Chen, Duo-Yao Kang, Kuen-Jong Lee · 2022
A scan-based test chip architecture composed of a two-dimensional array of C-testable blocks (CTBs) and scan registers is proposed, where each CTB contains several XOR modules and has the distinguished VH-bijection property, i.e., each CTB is bijective, and any change in either the vertical or horizontal input of a CTB will lead to changes in both vertical and horizontal outputs. We present a novel method to systematically embed each combinational standard cell in a cell library to an XOR module such that almost all input pattern faults (including all stuck-at faults) in the standard cells can be detected even if multiple faults exist. Great diagnosability is achieved due to the VH-bijection property of CTBs, the full fault coverage property for faults in the standard cells inside CTBs, and the scan-based test chip architecture.