Implementation of High Performance IEEE 754-Posit Conversion Hardware
Brett Mathis, James E. Stine · 2022
This paper demonstrates the implementation of conversion hardware between floating-point operands in the standardized IEEE 754 format to those in a Posit type-III unum format, as well as the reverse conversion from the Posit format to IEEE 754. High performance conversion between the two standards will encourage the use of dual-mode systems where IEEE 754 and Posit architectures can be used interchangeably when they are advantageous to each other, respectively. High performance, structural RTL architecture is shown in comparison to behavioral architecture in existing literature, yielding significant performance improvements. Synthesis comparisons to existing behavioral architectures are shown for standard IEEE 754 precisions and their closest Posit analogues. Results are given in cmos32soi32nm MTCMOS technology using ARM-based standard-cells and commercial EDA toolsets.