An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform
Hachem Bensalem, Yves Blaquière, Yvon Savaria · IEEE Transactions on Circuits & Systems II Express Briefs · 2022
This brief proposes and evaluates several OpenCL-based implementations of the Secure Hash Algorithm-3 (SHA-3) co-processor. These implementations are developed based on OpenCL optimization techniques and their impact on throughput and speedup are reported. The experimental results show that the proposed optimization techniques achieve a 310x speedup when compared to an unoptimized baseline implementation. Moreover, the best reported optimized SHA-3 co-processor achieves a 22.36 Gbps throughput, which is 2 times higher than the best previously published SHA-3 implemented using a high-level synthesis tool and even higher than the performance of most previously reported implementations developed using hardware description languages (HDLs). As a result, an efficient OpenCL-based SHA-3 co-processor suitable for FPGA platforms is proposed. To our knowledge, the reported SHA3 co-processor is the first OpenCL implementation targeting an FPGA-based edge computing platform.