Communication and Performance Trade-offs in a Systolic Machine
Denis Archambaud, Ivan Saraiva Silva, Pascal Faudemay · 1994
This paper presents the trade-offs concerning lnput-Output communications at the interface of a SIMD systolic machine, and inside the machine. These problems have been raised by the accelerating board we are currently designing. We discuss about the issues involved by VLSI design: cascadability, scalability, fault tolerance, and feasibility. We present the main features of our architecture, and the performances measured with an actual application which proves that despire of the host computer slowness, the I/O bottleneck is not a penalty for the calculation acceleration.