Low power and area efficient AES implementation using ROM based key expansion and rotational shift
Lokesh Polani, Karthi Balasubramanian, B. Yamuna, Talluri Venkata Sai · 2022
The tremendous increase in information transmission and data storage has lead to a high demand for secure information storage and transfer. Various security services for a wide range of applications use Advanced Encryption Standard (AES) as the default algorithm for encryption. With an ubiquitous access to information through mobile and handheld devices, the need for providing security with minimum area and power consumption is very essential. This paper deals with the design and implementation of a low power and area efficient AES architecture. This is achieved by avoiding the use of registers and using ROM during the sorting operation of AddRound keys and by merging of shift row operation and byte substitution. Further reduction in area and power is achieved by using a rotational shift instead of the standard cyclic shifting during the ShiftRow operation. The results from the study indicate that implementation of the proposed design on a Virtex-7 FPGA utilizes 62% less slice registers and 47% less slice LUTs as compared to the standard AES design. Moreover, calculation of power and area in 90 nm GPDK technology results in 30% reduced area and 75% less power.