A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation
Kyle Kuan, Tosiron Adegbija · 2022
This paper studies spin-transfer torque RAM (STTRAM) as an energy-efficient alternative to SRAM for implementing page walker caches (PWCs) in resource-constrained systems' memory management units. We analyze the access characteristics and persistence of PWC blocks in a set of multithreaded workloads, revealing that individual threads might have different runtime behaviors. Given this observation, we explore and analyze the benefits of heterogeneous retention time STTRAM-wherein STTRAM's data retention time is specialized to cache blocks' persistence needs-for implementing the PWC in multicore systems. Based on our analysis, we propose NECTAR, an energy-efficient heterogeneous STTRAM-based page walker cache architecture. Experimental results using multithreaded PARSEC benchmarks show that NECTAR enables runtime adaptability and offers substantial energy benefits for implementing the PWC, reducing the average energy by 81.36% compared to SRAM, without introducing significant overheads.