Resource-Efficient FPGA Implementation of Advanced Encryption Standard
Useok Lee, Ho Keun Kim, Young Jun Lim, Myung Hoon Sunwoo · 2022
Advanced encryption standard (AES) is today’s most widely used symmetric-key block cipher. This paper proposes an AES intellectual property (IP) design with high utilization efficiency of field-programmable gate array (FPGA). The round-based AES design is used to optimize the utilization of design resources. We analyzed and optimized MixColumns and SubBytes. In addition, we explored the tradeoff relationship between resource utilization and clock cycles in terms of the datapath variation of the round module. Based on the analysis, we propose an area-optimized AES implementation considering the characteristics of FPGA. The implementation results show up to 36% better look-up table (LUT) utilization efficiency than the Xilinx AES IP, and up to 17.9 times better than the existing AES implementation results.