DEFCON: Defect Acceleration through Content Optimization
Suriyaprakash Natarajan, Abhijit Sathaye, Chaitali S. Oak, Nipun Chaplot, Suvadeep Banerjee · 2022
During manufacturing of integrated circuits, it is imperative for cost and quality that defects that occur on die are screened early in the test process, preferably before packaging. As part of screening, stress steps are performed to accelerate latent defects so that they become observable and are detected by subsequent test steps. Traditionally, the levers for applying stress have been increased supply voltage and temperature while concurrently running a sliver of content that had been created to “test” defects. In this paper, we describe a methodology to generate content specifically targeting stress at latent defects by maximizing electrical activity. Our goal is to efficiently accelerate all classes of latent defects. This paper will give details of the technology and content generation methodology for scanned digital logic. Silicon results are provided on a recent client product. Ongoing work that extends this to address latent defects in other areas of the die are outlined.