A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test
Chan‐Ho Kye, Jihee Kim, Kyungmin Baek, Kahyun Kim, Sangjin Pack, Chang Won Jung, Deog‐Kyoon Jeong · 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC) · 2022
Many solutions for DRAM tests have been proposed to overcome the limitation of the low-performance automatic test equipment (ATE). Built-in-self-tester (BIST) has reduced the test burden for the high-cost ATE [1]. However, the test circuit burdens the area and power consumption of the DRAM, and the required functions not designed in the test circuit are difficult to test. Recently, a built-out tester (BOT) has been proposed to relieve the test circuit overhead in the DRAM and support high-speed tests [2–3]. It has the advantage of boosting maximum test speed with a low-speed ATE and reducing the pin costs of the ATE. Also, it performs myriad functions for DRAM read/write operations as a bridge between the ATE and the DRAM. Currently, as shown in Fig. 1(a), a data (DQ) test speed can be overcome by design for testability (DFT) implantation in the LPDDR5 DRAM. However, a data strobe (DQS) and write clock (WCK) test is difficult for applying DFT implantation.