Accelerated Piece-Wise-Linear Implementation Of Floating-Point Power Function
Raghavendra Nandagopal, V Rajashree, Madhav Rao · 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 2022
Power function is one of the elementary arithmetic operations, useful for wide variety of applications including image processing, signal processing, and recently neural network modules. Floating-point implementation preserves the capability of storing wide range of real numbers, when compared to fixed-point and integer data-format. In this work, power function ($X^{Y}$) is realized in floating-point format using logarithmic, and anti-logarithmic compute modules. The two inputs to the power function,$X$, and$Y$are floating-point representations, with the output realized with a precision of 3 and 5 decimal digits. A novel piece-wise-linear (PWL) method to approximately represent non-linear logarithmic and anti-logarithmic functions is proposed. The hardware design of power function in floating-point format is characterized in FPGA, and ASIC flow to extract hardware parameters. Subsequently error metrics are also characterized for this implementation. The synthesized results of the proposed function shows benefits in terms of compute-time over other implementations on FPGA, while preserving the precision. As per the authors knowledge, the power function design characteristics on silicon is presented for the first time.