Enhanced System Level Channel Characterization Methodology with Seamless Correlation among Hardware, Signal Integrity and Electrical Validation for Design Robustness
Jimmy Chun-Ming Hsu, Kuan-Ting Wu, Brian Ho, Lemon Lin, Betty Chen, Thonas Su, Steven Wu, Gary Hung, Jim Tseng · 2022
The proposed methodology demonstrates an effective approach to characterize channel design and closed-loop interactions between electrical validation and signal integrity. By combining the data measured by Intel ® Automatic In-Board Characterization (AIBC) [1] and the following electrical validation test results, it provides comprehensive correlation between signal integrity and electrical validation, which can efficiently clarify the root cause of issues. As a result, the overall debugging time and effort can decrease and thus accelerate customers’ PCB board development.