Data Synchronization in Non-Uniform Latency Custom DSP Designs
Samuel López-Asunción, Pablo Ituero, Marisa López‐Vallejo, Jesús Grajal · 2022
Many DSP algorithms for streams of constant-sample-rate data work by processing the signal by pieces, splitting the input signal into fixed-length blocks in order to calculate some parameter related to that chunk of signal. In custom multiblock DSP architectures, this kind of operations are laid out to be carried out in parallel. This poses a challenge since these operations may have greatly different latency values, so the data needs to be synchronized somehow for the following DSP block to acknowledge the results of the operations and keep on with the computation. In our proposal, we monitor the operations in order to synchronize the output data by storing the results until all operations are done. Every output is queued up in a FIFO structure so that when all the operations are complete the results can then be transferred to the next module simultaneously. The control structure is built so that the architecture also works when the signal blocks have variable length, or when the operations have variable latency. This approach allows for a reduction in the number of registers needed for a delay chain implementation, it is more flexible if the latency of the operations change, and can be easily updated if new operations are introduced. This architecture has been used and extensively tested in an Automatic Modulation Classifier implementation on an FPGA as part of a signal processing chain with parallel calculations of linear regressions and central moments of a constant-rate signal divided into blocks of different lengths.