CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level
Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, Toshinori Hosokawa · 2022
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attack, however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at gate level. In this paper, we propose a logic locking method based on SAT attack and FALL attack resistance at register transfer level.