Large Suppression to Lateral Charge Migration (LCM) Related Error Bits in Charge-Trap TLC 3D NAND Flash
Kenie Xie, Pena Guo, Fei Chen, Binglu Chen, Xiaotong Fang, Jixuan Wu, Xuepeng Zhan, Jiezhi Chen · 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) · 2022
We present a study to suppress error bits from lateral charge migration (LCM) in charge-trap (CT) 3D NAND flash memory. For the first time, a new Baking-and-Pre-read (BPR) method is proposed with combined long-time charge diffusion by baking and short-time stabilizing by Pre-read. By characterizing 96-layer Triple-level-cell (TLC) 3D NAND chips by the raw NAND chip tester, the storage stabilities, including data retention (DR) and read disturb (RD), are studied and it is found that DR/RD error bits can be reduced up to >70%, which could be explained by the large effects of suppression to LCM-related threshold voltage (Vth) down-shifts.