Cache-Major: A Hardware Architecture and Scheduling Policy for Improving DRAM Access Efficiency in GEMV
Jinhui Cheng, Xuanzhi Liu, Yue Cao, Wenjun Zhang, Zhongze Han, Bo Peng, Yixuan Liu, Donglin Zhang, Yongkang Han, Xiaoxin Xu, Jianguo Yang · 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) · 2022
The general matrix-vector multiplication (GEMV) is one of the most critical operations in HPC (high performance computing) researches and engineering applications, and is often used to evaluate the performance of a new architectural system. As the scale of the GEMV problem continues to expand, frequent out-of-order access to the DRAM gradually leads to the decrease of the system access bandwidth, which becomes the bottleneck to solve the GEMV efficiently. In this paper, we propose a high bandwidth cache designed in a highly customized memory controller and an efficient cache major scheduling policy which fully utilize DRAM address locality to achieve high-performance GEMV computation. The experimental results show that our proposed cache-major policy has reached a single-core sustained effective bandwidth of 112.34 MB/s (@2000× 2000, 32-bit float-point matrix), much better than baseline design and existing mature works.