A Fully Parallel On-Die ECC Architecture with High Area Reduction and RAS Enhancement for HBM3
Run-Jin Wu, Feng Chen, Cheng-Jer Yang, Feng Xu, One-Gyun Na, Ying-Qi Yang · 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) · 2022
This paper presents an efficient error-correction-code (ECC) scheme which is designed to enhance the Reliability, Availability, and Serviceability (RAS) features and save area for HBM3 DRAM, the latest-generation technology of high bandwidth memory (HBM). In order to improve reliability, a fully parallel Reed-Solomon (RS) encoder/decoder with the double-sub-engine architecture is proposed for the on-die ECC implementation where the symbol-wise interleaver/de-interleaver can provide significantly strong and flexible error correction capabilities. Furthermore, the area of the on-die ECC engine can be vastly reduced by introducing a hardware sharing scheme which can save 35% area overhead as compared to the conventional architecture. The on-die ECC has a symbol size of 8 bits and an ability of double-symbol-correction that can be implemented in future high performance memory systems.