Implementation of a RISC-V SMT Core in an AI processor
Hidetaro Tanaka, Tomoaki Tanaka, Ryosuke Higashi, Tsutomu Sekibe, Shuichi Takada, Hironori Nakajo · 2022
The RISC-V core, which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture, has been implemented. In the architecture, multiple types of engines specialized for different purposes are included. The RISC-V SMT core has the advantage of allowing multiple threads to execute simultaneously with a lower cost than that of simply using multiple cores. The RISC-V core supports operations of other engines under the SMT mechanism to be installed in “Chichibu,” which has been developed by ArchiTek Co., LTD as a multicore chip for edge artificial intelligence. In this implementation, we have reduced the hardware resource usage to less than half that of the previous implementation and exceeded the operating frequency of 100 MHz. In addition, the instructions per clock cycle (IPC) has been improved by approximately 66% using SMT.