Evolution of Efficient On-Chip Interconnect Architecture for SOC: A Review
Naman Batra, Brahmjit Singh · 2022 IEEE Global Conference on Computing, Power and Communication Technologies (GlobConPT) · 2022
Constant improvements in transistor technology have made it possible for computer design to support ever-increasing numbers of processing cores on a single silicon die. With the number of cores on a chip and complexity increasing, there is a greater need for on-chip communication capacity. As per recent research outcomes the packet-switched network-on-chip (NoC) proved to be a most scalable cores and low-cost communication fabric systems with dozens or even hundreds of processors' core. So, In this paper the performance, features, pros and cons of all the traditional on-chip interconnect architecture like Buses, Crossbar, Network-on-chip are reviewed. This is then followed by the review of the most frequent benefits and downsides of NoC's current power-saving practices.