An FPGA implementation of the VESA Display Stream Compression decoder
Nikolaos Kefalas, George Theodoridis · 2022
A HW architecture for the implementation of the DSC decoder is proposed. It demands 1 cycle/pixel (cpp) for 4:4:4 chroma sub-sampling format and 0.5 cpp for 4:2:2 or 4:2:0 formats. Also, it supports 3:1 lossless compression ratio and operates with sub-line latency. To achieve the above, specific optimizations have been applied at the algorithmic and design levels to efficiently distribute the operations on the pipeline stages and improve frequency. Its implementation on a Kintex Ultrascale+ device achieves at 262 MHz for 10-bit input sample, and it can process 32 High Dynamic Range (HDR) frames per second (Fps) for 4:4:4 chroma format and 60 HDR Fps for 4:2:2 or 4:2:0 formats.