FPGA Based Architecture for Test and Release of Custom Datapath in Pure RTL Designs
Boyko Baev Petrov · 2022
In pure RTL based design, the major difficulty is to prepare and provide a verification procedure on soft IDE in case of big quantities of test data. If the desire datapath is still unverified - this task will take many working time of high qualified RTL designers. In this paper an architecture method of processing and FPGA based board for test and release is described. It can decrease of working time of RTL designers in test and verification stages and time-to-market in release stage.