Work-in-Progress: RISC-V Based Low-cost Embedded Trace Processing System
Xiao Hu, Yaohua Wang, Xuan Gao · 2022
Although on-chip Trace debugging plays a key role in post-silicon debug and software optimizations, it suffers from massive trace information handling with limited on-chip hardware resources in embedded SoC processors. To this end, this paper proposes a Low-cost Embedded Trace Processing System (LE-TPS). LE-TPS employs a low-cost RISC-V core with customized trace handling instructions to exploit the underutilized resources of existing SoCs. This helps LE-TPS to collect, store and transmit the trace information in a way with low hardware cost, software independent feature, and minimal performance overhead. We believe that LE-TPS could be effective in post-silicon debug and software optimizations.