Inexact Floating-Point Multiplication Using Vedic Algorithm
S. Roobini Priya, P. Vanaja Ranjan · Research Square · 2022
Abstract This paper discusses on Vedic based floating point multiplication. The computations with integers representing very big or tiny numbers is cumbersome due to power aware designs required in IC designs. A good way to express integer values is using the IEEE 754 floating point encoding. DSP applications that use floating point numbers have a wide dynamic range of sophisticated computational processes that call for imprecise calculation techniques. This article describes the implementation and design of the Vedic multiplication and exact floating-point adder-based IEEE 754 channelized floating-point multiplier. The concepts in Vedic mathematics can be meritoriously used to improve logical sequences for implementing computational blocks in system on chip designs. Specific Vedic Sutras are discussed in this paper to implement and create the channelized floating-point multiplier according to IEEE 754. The multiplier's inputs are presented in IEEE 754 32-bit format. For mantissa multiplication, it uses the Urdhva Triyakbhyam sutra. Cases of underflow and overflow are handled through effective designs, to support design of pSoCs with power awareness.